This invention relates generally to control vectors in computer systems, and more particularly to providing exploitation of orthogonal control vectors in timing driven synthesis.
In modern, high frequency microprocessors, there are typically cycle limiting path(s). As such, the speed with which the logic on the given path can be executed determines the speed of the microprocessor. Therefore, fast execution of such a path yields a faster clock speed, which results in better performance.
If the path is in a custom dataflow macro, the circuit designer typically determines the design. In such circumstances, the designer executes the function implementing as few gates as possible. Since dataflow logic tends to be repetitive and straightforward, it is possible for the designer to generate the optimum solution. If the path is in a control macro, the task can be more complicated. Control logic tends to be more random than dataflow logic. As a result, timing driven synthesis tools are implemented to generate logic based on very high-speed integrated circuit (VHSIC) hardware description language (VHDL) written by a logic designer. The tool recognizes timing critical paths, based on timing assertions, and attempts to generate optimal logic on these paths in order to meet timing. Thus, in the case of a cycle limiting path in a control macro, the synthesis tool is the determining factor.
However, the solution generated by synthesis may not be the minimal solution. Frequently, the synthesis tool is unable to recognize cases that can never occur. Designing a chip with a non-minimal cycle limiting path is unacceptable. As such, the logic designer, in order to help synthesis along, must be able to help synthesis recognize and exploit the quirks of the controls, which allows synthesis to regenerate a more optimal solution.